Phase difference detectors

ABSTRACT

This invention provides a phase difference detector for detecting when the phase relationship between two waves changes from a predetermined relationship by a predetermined amount. Delay means are provided for relatively delaying the two waves to an extend dependent upon the lead or lag tolerance permitted in the phase relationship between the two waves, and a JK flip-flop circuit is provided to one data input terminal of which one of the two relatively delayed waves are applied and to the other data input terminal of which the same wave inverted is applied. The other of the delayed waves is applied to the sampling input terminal of said circuit.

United States Patent inventor Appl. No.

Filed Patented Assignee Priority Colin Graham White PHASE DIFFERENCEDETECTORS 2 Claims, 2 Drawing Figs.

U.S. Cl 328/133, 307/232, 307/295, 324/83 D Int. Cl H0311 13/00 Field ofSearch 307/232,

WA VE SOURCE SOURCE Primary Examiner-Stanley T. KrawczewiczAttorney-Baldwin, Wight and Brown ABSTRACT: This invention provides aphase difference detector for detecting when the phase relationshipbetween two waves changes from a predetermined relationship by apredetermined amount. Delay means are provided for relatively delayingthe two waves to an extend dependent upon the lead or lag tolerancepermitted in the phase relationship between the two waves, and a JKflip-flop circuit is provided to one data input terminal of which one ofthe two relatively delayed waves are applied and to the other data inputterminal of which the same wave inverted is applied. The other of thedelayed waves is applied to the sampling input terminal of said circuit.

PATENTED AUB17|971 3600.690

WAVE 5,. sou/205 DELAY k 12 4\ {2 a 15 WAVE SOURCE DELAY LA 13 FIG. I

INVENTOR PHASE DIFFERENCE DETECTORS This invention relates to phasedifference detectors and more particularly to phase difference detectorsfor detecting phase difference between two similar wave trains.

It is often required to provide some means of indicating when the phaserelation between two wave trains changes beyonda certain tolerance Thisis the case for example in an electronic circuit relying upon the outputof a clock oscillator, whose output requires to bear, within apredetermined tolerance, a fixed relation to a reference oscillator.Similar requirements arise in so-called multiple clock oscillatorsystems, when the outputs of two or more clock oscillators require to bemonitored and an indication given when their outputs depart from eachother by a predetermined amount. The present invention seeks to providean improved phase difference detector suitable for use in arrangementssuch as are exemplified above.

According to this invention a phase difference detector for detectingwhen the phase relationship between two waves changes from apredetermined relationship by a predetermined amount includes means forrelatively delaying said waves to an extent dependent upon the lead orlag tolerance permitted in the phase relationship between the two waves,a J K flip-flop or like circuit, means for applying one of said tworelatively delayed waves to one data input terminal of said circuit,means for inverting said one wave and applying it to the other datainput terminal of the circuit and means for applying the other of saidtwo relatively delayed waves to the sampling input terminal of saidcircuit.

Preferably the detector includes a second JK flip-flop or similarcircuit, means for applying the said other wave to one data inputterminal of the second circuit, means for inverting said other wave andapplying it to the other data input terminal of the second circuit andmeans for applying the said one wave to the sampling input terminal ofsaid second circuit.

The invention is illustrated in and further described with reference tothe accompanying drawing in which FIG. 1 illustrates a phase differencedetector in accordance with the present invention and FIG. 2 shows onepossible alternative for each of the J K flipflop circuits used in thearrangement of FIG. 1.

Referring to FIG. 1 it is assumed that it is desired to indicate whenthe relative phase of the output waves, assumed to be square waveshaving a mark/space ratio of unity for ease of explanation, slip out ofphase by more than a predetermined extent. The two wave sources areshown at l and 2 respectively. Output square waves from wave source 1are applied via a first delay unit 2 directly to one data input terminal3 of a first J K flip-flop'circuit 4 and also via an inverting circuit 5to the other data input terminal 6 of the .I K flip-flop circuit 4.Output waves from the wave source 2 are applied through a second delayunit 7 directly to the first data input terminal 8 of a further JKflip-flop circuit 9 and via a further inverting circuit 10 to the otherdata input terminal 1 1 of the 1K FLIP-flop circuit 9. The samplinginput terminal 12 is connected to have undelayed waves from source 2applied to it whilst the sampling input terminal 13 of IX flip-flopcircuit 9 is connected to have undelayed waves from wave source 1applied to it. As illustrated, a 1 condition appearing on output lead 14of JK flip-flop circuit 4 will indicate that the wave form from source 1is leading the wave form from source 2 by more than a predeterminedamount equal to the delay provided by delay unit 2. A 1 output on outputterminal 15 of JK flip-flop circuit 9 indicates that the waveform fromsource 2 is leading the wave form from source 1 by more than apredetermined extent equal to the delay provided by delay unit 7.Usually, of course, the delays provided by the two delay units will besimilar since normally the lead and lag tolerances are similar.

The operation of the circuit of FIG. 1 is as follows. The output wavetrains from wave sources 1 and 2 are similar. At JK flip-flop circuit 4a delayed version of the waveform from source 1 is resented forsampling. The wave train from source 2, app red to the sampling inputterminal of the JK flipflop circuit 4 samples the wave train fromsource 1. As is known, either positive going or negative going edges maybe employed to sample the data applied to the data input terminals of aJK flip-flop circuit in dependence upon the nature of the circuit. Inthe present case positive going edge sampling will be considered. In thewave form diagram shown adjacent JK flip-flop circuit 4, W is thedelayed version of the wave form from wave source 1 sampled by the waveform W So long as source 1 and source 2 are in phase the result of Wsampling W will be a 0" at the output terminal 14 of JK flip-flopcircuit 4. If however source 1 leads source 2 by more than the delay ofdelay unit 2 together with the bistable sampling time, the result ofsampling will be a 1" appearing on output terminal 14.

Similarly, when source 2 leads source 1 by more than the delay time ofdelay unit 7 and the bistable sampling time a 1 will be indicated on theoutput terminal 15 of J K flip-flop circuit 9.

FIG. 2 shows an interconnected configuration of NAND gates which may beused to replace either of the .IK flip-flop circuits 4 or 9 in FIG. 1.Like terminal references are used in FIG. 2 to denote like terminals ofJ K flip-flip circuit 4 in FIG. 1.

Iclaim:

1. A phase difference detector for detecting when the phase relationshipbetween two waves changes from a predetermined relationship by apredetermined amount, means for relatively delaying said waves to anextent dependent upon the lead or lag tolerances permitted in the phaserelationship between the two waves, a JK flip-flop or like circuit,means for applying one of said two relatively delayed waves to one datainput terminal of said circuit, means for inverting said one wave andapplying it to the other data input terminal of the circuit and meansfor applying the other of said two relatively delayed waves to thesampling input terminal of said circuit.

2. A detector as claimed in claim 1 and including a ScCul'lU JKflip-flop or similar circuit, means for applying the said other wave toone data input terminal of the second circuit. means for inverting saidother wave and applying it to the other data input terminal of thesecond circuit and means for applying the said one wave to the samplinginput terminal of said second circuit.

1. A phase difference detector for detecting when the phase relationshipbetween two waves changes from a predetermined relationship by apredetermined amount, means for relatively delaying said waves to anextent dependent upon the lead or lag tolerances permitted in the phaserelationship between the two waves, a JK flip-flop or like circuit,means for applying one of said two relatively delayed waves to one datainput terminal of said circuit, means for inverting said one wave andapplying it to the other data input terminal of the circuit and meansfor applying the other of said two relatively delayed waves to thesampling input terminal of said circuit.
 2. A detector as claimed inclaim 1 and including a second JK flip-flop or similar circuit, meansfor applying the said other wave to one data input terminal of thesecond circuit, means for inverting said other wave and applying it tothe other data input terminal of the second circuit and means forapplying the said one wave to the sampling input terminal of said secondcircuit.